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FEATURES * * * * * * * * *
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Four Quadrant Multiplication 16-Bit Monotonicity Lower Data Bus Feedthrough @ CS = 1 Low Feedthrough Error Low Power Consumption TTL/5 V CMOS Compatible Double Buffered Decoded DAC Approach Latch-Up Free
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MP7636A
15 V CMOS Microprocessor Compatible Double-Buffered, Multiplying 16-Bit Digital-to-Analog Converter
BENEFITS * High Accuracy Performance at Low Cost * Easy Interface with 8-Bit Microprocessors * Simple Upgrade of MP1230A Family to High Accuracy (Pin Compatible) * Reduced Board Space * 16-Bit Bus Version: MP7626
GENERAL DESCRIPTION
The MP7636A is manufactured using advanced thin film resistors on a double metal CMOS process. The MP7636A incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 16-bit differential non-linearity is achieved with minimal laser trim. The MP7636A is packaged in a 20-pin 300 mil wide DIP and is a direct 16-bit replacement for the 12-bit DAC1230 series. Full
pin-for-pin compatibility allows existing systems to be upgraded to 16 bits without hardware modification. The MP7636A provides 16-bit data loading through 8 input data lines for direct interface to 8-bit data buses. All data loading and data transfer operations are identical to the WRITE cycle of a static RAM. The MP7636A uses a unique circuit which significantly reduces transients in the supplies during DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
DB15 (MSB) (DB7) DB14 (DB6) DB13 (DB5) DB12 (DB4) DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB)
When LE = 1 latch outputs follow inputs When LE = 0 Latch outputs are latched
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8-Bit Input Latch
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16-Bit Register
16-Bit MDAC
RFB IOUT1 IOUT2
8-Bit Input Latch
BYTE1/BYTE2 CS WR1 XFER WR2
LE
VDD
VREF
DGND
Rev. 2.00 1
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AGND
MP7636A
ORDERING INFORMATION
Package Type
SOIC SOIC
Temperature Range
-40 to +85C -40 to +85C
Part No.
MP7636AJS MP7636AKS
INL (LSB)
+4 +2
DNL (LSB)
+4 +2
Gain Error (% FSR)
0.1 0.1
*Contact factory for non-compliant military processing
PIN CONFIGURATION
See Packaging Section for Package Dimensions
CS WR1 AGND DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0, LSB) VREF RFB DGND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD BYTE1/BYTE2 WR2 XFER DB12 (DB4) DB13 (DB5) DB14 (DB6) DB15 (MSB) (DB7) IOUT2 IOUT1
20 Pin SOIC (Jedec, 0. 300") S20
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 NAME CS WR1 AGND DB11 (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0) VREF RFB DGND IOUT1 DESCRIPTION Chip Select (Active Low) Write1 (Active Low) Analog Ground Data Input Bit 11 (MSB) Data Input Bit 3 Data Input Bit 10 Data Input Bit 2 Data Input Bit 9 Data Input Bit 1 Data Input Bit 8 Data Input Bit 0 (LSB) Reference Input Voltage Internal Feedback Resistor Digital Ground Current Output 1 20 14 15 16 17 18 19 PIN NO. 12 13 NAME IOUT2 DB15 (MSB) (DB7) DB14 (DB6) DB13 (DB5) DB12 (DB4) XFER WR2 BYTE1/ BYTE2 VDD DESCRIPTION Current Output 2 Data Input Bit 15 (Most Significant Bit) Data Input Bit 7 Data Input Bit 14 Data Input Bit 6 Data Input Bit 13 Data Input Bit 5 Data Input Bit 12 Data Input Bit 4 Transfer Control Signal (Active Low) Write 2 (Active Low) Byte Sequence Control
Power Supply
Rev. 2.00 2
MP7636A
ELECTRICAL CHARACTERISTICS
(VDD = + 15 V, VREF = +10 V unless otherwise noted)
25C Typ Tmin to Tmax Min Max
Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J, S K, L, T Differential Non-Linearity J, S K, T L Gain Error Gain Temperature Coefficient2 Power Supply Rejection Ratio
Symbol
Min
Max
Units
Test Conditions/Comments FSR = Full Scale Range
N INL
16
16
Bits LSB Best Fit Straight Line Spec. (Max INL - Min INL) / 2
+4 +2 DNL +4 +2 +1 GE TCGE PSRR +50 +0.1
+4 +2 LSB +4 +2 +2 +0.1 +2 +50 % FSR ppm/C ppm/% All grades guaranteed monotonic over full operating temperature range. Using Internal RFB Gain/Temperature |Gain/VDD| VDD = + 5% IOUT1 only
Output Leakage Current DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1
IOUT
+10
+200
nA
tS FT
2 2
s mV p-p
To 1/2 LSB RL=100, CEXT=13pF VREF = 20 V p-p Sine wave @ 10kHz
REFERENCE INPUT Input Resistance LOGIC INPUTS3 Input High Voltage Input Low Voltage Input Current Input Capacitance Data Control ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 280 120 100 240 pF pF pF pF DAC all 1's DAC all 0's DAC all 1's DAC all 0's VINH VINL ILKG CIN CIN 3.0 2.4 0.8 +1 5 5 3.0 0.8 +1 V V A pF pF RIN 2.5 7.5 2.5 7.5 k
Rev. 2.00 3
MP7636A
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter POWER SUPPLY5 Functional Voltage Range2 Supply Current SWITCHING CHARACTERISTICS2, 4 CS to WR Set-Up Time CS to WR Hold Time Data Valid to WR Set-Up Time Data Valid to WR Hold Time WR, XFER Pulse Width NOTES: (1) (2) (3) (4) (5) Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice tCS tCH tDS tDH tW 150 10 70 70 150 ns ns ns ns ns VDD IDD 4.5 16.5 1 5.0 16.5 1 V mA Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
All digital inputs 0 V or VDD
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3
Voltage at Any Digital Input . . . . . GND -0.5 to VDD +0.5 V Voltage at VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V DC Voltage Applied to IOUT1 or IOUT2 GND -0.5 V to +17 V Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . +17 VDC
1
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature Range . . . . . . . . . . . . -65C to 150C Package Power Dissipation Rating to 75C SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . . . . 12mW/C
NOTES: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 GND refers to AGND and DGND.
APPLICATION NOTES Refer to Section 8 for Applications Information
Rev. 2.00 4
MP7636A
TIMING DIAGRAM
VIH CS, BYTE1/BYTE2 VIL tW 50% VIL VIH DATA BITS VIL tS IOUT1, IOUT2 SETTLED TO +0.01% 50% tDS 50% 50% tCS tCH 50%
VIH WR
tDH 50%
DEFINITION OF CONTROL SIGNALS:
CS: WR1: Chip Select (Active low). It will enable WR1. Write 1 (Active low) The WR1 is used to load the digital data bits (DB) into the input latch.
IOUT2:
DAC Current Output 2 Bus. IOUT2 is a complement of IOUT1. The ladder termination has been tied to IOUT2 internally. Feedback Resistor. This internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the DAC and tracks these resistor over temperature. Reference Voltage Input. This input connects an external precision voltage source to the internal DAC. The VREF can be selected over the range of +25V to -25V or the analog signal for a 4-quadrant multiplying mode application. Power Supply Voltage. This is the power supply pin for the part. The VDD can be from +5 V DC to +15 V DC, however optimum voltage is +15 V DC.
RFB:
BYTE1/BYTE2: Byte sequence control. The BYTE1/BYTE2 control pin is used to select MSB and LSB both input latches. WR2: XFER: Write 2 (Active low). It will enable XFER. Transfer control signal (Active low). This signal, in combination with WR2, causes the 16-bit data which is available in the input latches to transfer to the DAC register.
VREF:
VDD:
DB0 to DB15: Digital Inputs. DB0 is the least significant digital input (LSB) and DB15 is the most significant digital input (MSB). IOUT1: DAC Current Output 1 Bus. IOUT1 is a maximum for a digital code of all 1's in the DAC register, and is zero for all 0's in the DAC register.
AGND: Analog Ground. Back gate of the DAC N-channel current steering switches. DGND: Digital Ground . The timing diagrams for updating the DAC register are shown in Figures 1 and 2.
Rev. 2.00 5
MP7636A
DATA BUS Valid Valid
CS
BYTE1/BYTE2
WR1 XFER + WR2
Analog Output Updated
Analog Output Latched
Load 8-bit (MSB) Input Latch 8-bit (LSB) Input Latch also changed
Overwrite 8-bit (LSB) Input Latch
Transfer 16-bit word to the DAC Register (Analog Output Updated) and Latched
Figure 1. Typical Interface with an 8-bit Data Bus
DATA BUS
Valid
Valid
CS
BYTE1/BYTE2 + XFER WR1 + WR2
Analog Output Updated
Analog Output Latched
Load 8-bit (MSB) Input Latch 8-bit (LSB) Input Latch also changed
Overwrite the 8-bit (LSB) Input Latch and Transfer all 16 bits word to the DAC Register
Figure 2. Automatic Transfer
Rev. 2.00 6
MP7636A
20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20
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20
11
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h x 45 C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.500 0.292 MAX 0.104 0.0115 0.019 0.0125 0.510 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 12.70 7.42 MAX 2.642 0.292 0.483 0.318 12.95 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 2.00 7
MP7636A
PERFORMANCE CHARACTERISTICS
LSB
Graph 1. Relative Accuracy vs. Digital Code
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 8

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